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7c371: Tuesday, May 26, 1992 Revision: August 9, 1995
CY7C371
UltraLogict 32 Macrocell Flash CPLD
Features Functional Description
D D D D D
32 macrocells in two logic blocks 32 I/O pins 6 dedicated inputs including 2 clock pins No hidden delays High speed fMAX = 143 MHz tPD= 8.5 ns tS = 5 ns tCO = 6 ns
The CY7C371 is a Flash erasable Complex Programmable Logic Device (CPLD) and is part of the FLASH370 family of high den sity, high speed CPLDs. Like all members of the FLASH370 family, the CY7C371 is designed to bring the ease of use and high performance of the 22V10 to high density CPLDs. The 32 macrocells in the CY7C371 are di vided between two logic blocks. Each logic block includes 16 macrocells, a 72 x 86 product term array, and an intelligent product term allocator. The logic blocks in the FLASH370 architec ture are connected with an extremely fast and predictable routing resource the Programmable Interconnect Matrix
(PIM). The PIM brings flexibility, rout ability, speed, and a uniform delay to the interconnect. Like all members of the FLASH370 family, the CY7C371 is rich in I/O resources. Each macrocell in the device features an associated I/O pin, resulting in 32 I/O pins on the CY7C371. In addition, there are four dedicated inputs and two input/clock pins. Finally, the CY7C371 features a very sim ple timing model. Unlike other high den sity CPLD architectures, there are no hid den speed delays such as fanout effects, in terconnect delays, or expander delays. Re gardless of the number of resources used or the type of application, the timing pa rameters on the CY7C371 remain the same.
D D D
Electrically alterable FLASH technology Available in 44 pin PLCC, CLCC, and TQFP packages Pin compatible with the CY7C372
Logic Block Diagram
INPUTS CLOCK INPUTS 4 INPUT MACROCELLS 2 INPUT/CLOCK MACROCELLS
2
2
PIM
16 I/Os I/O0-I/O15
LOGIC BLOCK A 16 16 36 36
LOGIC BLOCK B
16 I/Os I/O16-I/O31
16
16
7c371 1
Selection Guide
7C371-143 7C371-110 7C371-83 7C371L-83 7C371-66 7C371L-66
Maximum Propagation Delay, tPD (ns) Minimum Set Up, tS (ns) Maximum Clock to Output, tCO (ns) Maximum Supply Current, Current ICC (mA) Commercial Military/Ind.
8.5 5 6 220
10 6 6.5 175
12 10 10 175 220
12 10 10 90 110
15 12 12 175 220
15 12 12 90 110
Shaded area contains preliminary information.
Cypress Semiconductor Corporation
D
3901 North First Street 1
D
San Jose
D
CA 95134
D
408-943-2600
December 1993 - Revised August 1995
7c371: Tuesday, May 26, 1992 Revision: August 9, 1995
CY7C371
Pin Configurations
PLCC/CLCC Top View
4 3 2 31 30 29 28 I/O I/O I/O GND CC
TQFP Top View
31 30 29 I/O GND I/O I/O CC I/O I/O I/O 28 1 0
4
3
2
1
0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V
6
5
4
3
2
1
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 I/O27 I/O26 I/O25 I/O24 CLK1/I5 GND I4 I3 I/O23 I/O22 I/O21 I/O5 I/O6 I/O7 I0 I1 GND CLK0/I2 I/O8 I/O9 I/O10 I/O11 1 2 3 4 5 6 7 8 9
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 I/O27 I/O26 I/O25 I/O24 CLK1/I5 GND I4 I3 I/O23 I/O22 I/O21
I/O5 I/O6 I/O7 I0 I1 GND CLK0/I2 I/O8 I/O9 I/O10 I/O11
7 8 9 10 11 12 13 14 15 16 17
10 11
18 19 20 21 22 23 24 25 26 27 28 7c371 2 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 CC GND
12 13 14 15 16 17 18 19 20 21 22 7c371 3 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 GND CC
V
Logic Block
The number of logic blocks distinguishes the members of the FLASH370 family. The CY7C371 includes two logic blocks. Each logic block is constructed of a product term array, a product term allocator, and 16 macrocells.
product term allocation is handled by software and is invisible to the user.
I/O Macrocell
Product Term Array
The product term array in the FLASH370 logic block includes 36 in puts from the PIM and outputs 86 product terms to the product term allocator. The 36 inputs from the PIM are available in both positive and negative polarity, making the overall array size 72 x 86. This large array in each logic block allows for very complex func tions to be implemented in a single pass through the device.
Each of the macrocells on the CY7C371 has a separate associated I/O pin. The input to the macrocell is the sum of between 0 and 16 product terms from the product term allocator. The macrocell in cludes a register that can be optionally bypassed. It also has polar ity control, and two global clocks to trigger the register. The ma crocell also features a separate feedback path to the PIM so that the register can be buried if the I/O pin is used as an input.
Programmable Interconnect Matrix
Product Term Allocator
The product term allocator is a dynamic, configurable resource that shifts product terms to macrocells that require them. Any number of product terms between 0 and 16 inclusive can be as signed to any of the logic block macrocells (this is called product term steering). Furthermore, product terms can be shared among multiple macrocells. This means that product terms that are com mon to more than one output can be implemented in a single prod uct term. Product term steering and product term sharing help to increase the effective density of the FLASH370 CPLDs. Note that
Maximum Ratings
The Programmable Interconnect Matrix (PIM) connects the two logic blocks on the CY7C371 to the inputs and to each other. All inputs (including feedbacks) travel through the PIM. There is no speed penalty incurred by signals traversing the PIM.
Design Tools
Development software for the CY7C371 is available from Cy press's and software packages. All of these products are based on the IEEE standard VHDL language. Cy press also actively supports third party design tools such as ABELt, CUPLt, MINC, and LOG/iCt. Please contact your lo cal Cypress representative for further information.
Warp2, Warp2+,
V
Warp3
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature . . . . . . . . . . . . . . . . . . . -65_C to +150_C Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . -55_C to +125_C Supply Voltage to Ground Potential . . . . . . . . . -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V DC Program Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5V Output Current into Outputs (LOW) . . . . . . . . . . . . . . . 16 mA
Note:
Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . . . >2001V (per MIL STD 883, Method 3015) Latch Up Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . >200 mA
Operating Range
Ambient Range Temperature VCC
Commercial Military[1] Industrial
0_C to +70_C -55_C to +125_C -40_C to +85_C
V
5V 5% 5V 10% 5V 10%
1.
TA is the instant on" case temperature.
2
7c371: Tuesday, May 26, 1992 Revision: August 9, 1995
CY7C371
Electrical Characteristics
Parameter
Over the Operating Range[2]
Test Conditions Min. Max. Unit
Description
VOH VOL VIH VIL IIX IOZ IOS ICC
Output HIGH Voltage
VCC = Min. Min VCC = Min. Min
IOH = -3.2 mA (Com'l/Ind) IOH = -2.0 mA (Mil) IOL = 16 mA (Com'l/Ind) IOL = 12 mA (Mil) Input Logical HIGH Voltage for all inputs[3] inputs[2]
2.4
V V 0.5 V V
Output LOW Voltage
Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Output Short Circuit Current[4, 5] Power Supply Current
Guaranteed GND
2.0 -0.5 -10 -50 -30
7.0 0.8 +10 +50 -90 175 90 220 110
V V
Guaranteed Input Logical LOW Voltage for all
V V
I
CC
mA mA
mA mA
GND < VO < VCC, Output Disabled VCC = Max., VOUT = 0.5V VCC = Max., IOUT = 0 mA, f = 1 mHz, VIN = GND, VCC[6] mHz GND Com'l Com'l L " -66, -83 Com'l-143, Mil/Ind Ind L -66, -83 "
Capacitance
[4]
Description Test Conditions Max. Unit
Parameter
CIN COUT
Input Capacitance Output Capacitance
[4]
VIN = 5.0V at f=1 MHz VOUT = 5.0V at f = 1 MHz
10 12
pF pF
Endurance Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
N
Notes:
Minimum Reprogramming Cycles
Normal Programming Conditions
4. 5.
100
Cycles
1. 2. 3.
See the last page of this specification for Group A subgroup testing in formation. These are absolute values with respect to device ground. All over shoots due to system or tester noise are included. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been cho sen to avoid test problems caused by tester ground degradation.
Tested initially and after any design or process changes that may affect these parameters. Measured with 16 bit counter programmed into each logic block.
3
7c371: Tuesday, May 26, 1992 Revision: August 9, 1995
CY7C371
AC Test Loads and Waveforms
238W (COM'L) 319W (MIL) 5V OUTPUT 35 pF INCLUDING JIG AND SCOPE
(a)
238W (COM'L) 319W (MIL) 5V OUTPUT
170W (COM'L) 236W (MIL) JIG AND SCOPE
170W (COM'L) 5 pF 236W (MIL)
INCLUDING
7c371 4 7c371 5
(b)
ALL INPUT PULSES 3.0V 90% 10% 2.08V (COM'L) 2.13V (MIL) GND < 2 ns < 2 ns 90% 10%
Equivalent to:
THEVENIN EQUIVALENT 99W (COM'L) 136W (MIL)
OUTPUT
(c)
7c371 6
Parameter
VX
Output Waveform
Measurement Level
tER (-) tER (+) tEA (+) tEA (-)
1.5V
VOH
0.5V 0.5V
VX VX
7c371 7
2.6V
VOL
7c371 8
1.5V
VX VX
0.5V
VOH
7c371 9
Vthc
0.5V
(d) Test Waveforms
VOL
7c371 10
Switching Characteristics
Over the Operating Range[7]
7C371-83 7C371-143 7C371-110 Min. Max. 7C371L-83 Min. Max. 7C371-66 7C371L-66 Min. Max. Unit
Parameter
Description
Min.
Max.
Combinatorial Mode Parameters
tPD tPDL tPDLL tEA tER tWL tWH tIS tIH tICO tICOL
Input to Combinatorial Output Input to Output Through Transparent Input or Output Latch Input to Output Through Transparent Input and Output Latches Input to Output Enable Input to Output Disable Clock or Latch Enable Input LOW Time[4] Clock or Latch Enable Input HIGH Time[4] Input Register or Latch Set Up Time Input Register or Latch Hold Time Input Register Clock or Latch Enable to Combina torial Output Input Register Clock or Latch Enable to Output Through Transparent Output Latch
8.5 11.5 13.5 13 13
10 13 15 14 14
12 18 20 19 19
15 22 24 24 24
ns ns ns ns ns
Input Registered/Latched Mode Parameters
2.5 2.5 2 2 12 14
3 3 2 2 14 16
4 4 3 3 19 21
5 5 4 4 24 26
ns ns ns ns ns ns
Shaded area contains preliminary information.
Note:
6.
All AC parameters are measured with 16 outputs switching.
7.
This specification is intended to guarantee interface compatibility of the other members of the CY7C370 family with the CY7C371. This specification is met for the devices operating at the same ambient tem perature and at the same power supply voltage.
4
7c371: Tuesday, May 26, 1992 Revision: August 9, 1995
CY7C371
Switching Characteristics
Over the Operating Range[6] (continued)
Parameter Description Output Registered/Latched Mode Parameters
tCO tS tH tCO2 tSCS tSCS2 tSL tHL fMAX1 fMAX2 Clock or Latch Enable to Output Set Up Time from Input to Clock or Latch Enable Register or Latch Data Hold Time Output Clock or Latch Enable to Output Delay (Through Memory Array) Output Clock or Latch Enable to Output Clock or Latch Enable (Through Memory Array) Output Clock Through Array to Output Clock (2 Pass Delay)[4] Set Up Time from Input Through Transparent Latch to Output Register Clock or Latch Enable Hold Time for Input Through Transparent Latch from Output Register Clock or Latch Enable Maximum Frequency with Internal Feedback (Least of 1/tSCS, 1/(tS + tH), or 1/tCO)[4] Maximum Frequency Data Path in Output Regis tered/Latched Mode (Lesser of 1/(tWL + tWH), 1/(tS + tH), or 1/tCO)[4] Maximum Frequency with external feedback (Lesser of 1/(tCO + tS) and 1/(tWL + tWH))[4] Output Data Stable from Output clock Minus Input Register Hold Time for 7C37x[4, 8]
7C371-83 7C371-66 7C371-143 7C371-110 7C371L-83 7C371L-66 Min. Max. Min. Max. Min. Max. Min. Max. Unit
6 5 0 12 7 13 9 0 143 9 16.5 10 0 111 153.8 6 0 14 12 21 12 0 83.3 100 6.5 10 0 19 15 27 15 0 66.6 83.3 10 12 0 24 12 ns ns ns ns ns ns ns ns MHz MHz
166.7
fMAX3 tOH-tIH 37x
91 0
80 0
50 0
41.6 0
MHz ns
Pipelined Mode Parameters
tICS fMAX4
Input Register Clock to Output Register Clock Maximum Frequency in Pipelined Mode (Least of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH), or 1/tSCS) Asynchronous Reset Width[4] Asynchronous Reset Recovery Time[4] Asynchronous Reset to Output Asynchronous Preset Width[4] Asynchronous Preset Recovery Time Asynchronous Preset to Output Power On Reset[4]
[4]
7 125
9 111
12 76.9
15 62.5
ns MHz
Reset/Preset Parameters
tRW tRR tRO tPW tPR tPO tPOR
8 10 14 8 10 14 1
10 12 16 10 12 16 1
15 17 21 15 17 21 1
20 22 26 20 22 26 1
ns ns ns ns ns ns
ms
Shaded area contains preliminary information.
Switching Waveforms
Combinatorial Output
INPUT
tPD
COMBINATORIAL OUTPUT
7c371 11
5
7c371: Tuesday, May 26, 1992 Revision: August 9, 1995
CY7C371
Switching Waveforms (continued)
Registered Output
INPUT
tS
tH
CLOCK
tCO
REGISTERED OUTPUT
tWH
tWL
CLOCK
7c371 12
Latched Output
INPUT tS tH
LATCH ENABLE
tPDL
tCO
LATCHED OUTPUT
7c371 13
Registered Input
REGISTERED INPUT
tIS
tIH
INPUT REGISTER CLOCK tICO
COMBINATORIAL OUTPUT
tWH
tWL
CLOCK
7c371 14
6
7c371: Tuesday, May 26, 1992 Revision: August 9, 1995
CY7C371
Switching Waveforms (continued)
Clock to Clock
REGISTERED INPUT
INPUT REGISTER CLOCK tICS tSCS
OUTPUT REGISTER CLOCK
7c371 15
Latched Input
LATCHED INPUT
tIS
tIH
LATCH ENABLE
tPDL
tICO
COMBINATORIAL OUTPUT
tWH
tWL
LATCH ENABLE
7c371 16
Latched Input and Output
LATCHED INPUT
tPDLL
LATCHED OUTPUT
tICOL INPUT LATCH ENABLE
tSL tHL
tICS OUTPUT LATCH ENABLE
tWH
tWL
LATCH ENABLE
7c371 17
7
7c371: Tuesday, May 26, 1992 Revision: August 9, 1995
CY7C371
Switching Waveforms (continued)
Asynchronous Reset
tRW
INPUT
tRO
REGISTERED OUTPUT
tRR
CLOCK
7c371 18
Asynchronous Preset
tPW
INPUT
tPO
REGISTERED OUTPUT
tPR
CLOCK
7c371 19
Power Up Reset Waveform
90% VCC
POWER SUPPLY VOLTAGE
10%
tPOR REGISTERED ACTIVE LOW OUTPUTS tS
CLOCK
tPOR MAX = 1
ms
tWL
7c371 20
Output Enable/Disable
INPUT
tER
tEA
OUTPUTS
7c371 21
8
7c371: Tuesday, May 26, 1992 Revision: August 9, 1995
CY7C371
Ordering Information
Speed (MHz) Ordering Code Package Name Package Type Operating Range
143 110 83
66
Shaded areas contain preliminary information.
MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics
Parameter Subgroups
CY7C371-143AC CY7C371-143JC CY7C371-110AC CY7C371-110JC CY7C371-83AC CY7C371L-83AC CY7C371-83JC CY7C371L-83JC CY7C371-83AI CY7C371L-83AI CY7C371-83JI CY7C371L-83JI CY7C371-83YMB CY7C371-66AC CY7C371L-66AC CY7C371-66JC CY7C371L-66JC CY7C371-66AI CY7C371L-66AI CY7C371-66JI CY7C371L-66JI CY7C371-66YMB
A44 J67 A44 J67 A44 A44 J67 J67 A44 A44 J67 J67 Y67 A44 A44 J67 J67 A44 A44 J67 J67 Y67
44 Lead Thin Plastic Quad Flat Pack 44 Lead Plastic Leaded Chip Carrier 44 Lead Thin Plastic Quad Flat Pack 44 Lead Plastic Leaded Chip Carrier 44 Lead Thin Plastic Quad Flat Pack 44 Lead Thin Plastic Quad Flat Pack 44 Lead Plastic Leaded Chip Carrier 44 Lead Plastic Leaded Chip Carrier 44 Lead Thin Plastic Quad Flat Pack 44 Lead Thin Plastic Quad Flat Pack 44 Lead Plastic Leaded Chip Carrier 44 Lead Plastic Leaded Chip Carrier 44 Lead Ceramic Leaded Chip Carrier 44 Lead Thin Plastic Quad Flat Pack 44 Lead Thin Plastic Quad Flat Pack 44 Lead Plastic Leaded Chip Carrier 44 Lead Plastic Leaded Chip Carrier 44 Lead Thin Plastic Quad Flat Pack 44 Lead Thin Plastic Quad Flat Pack 44 Lead Plastic Leaded Chip Carrier 44 Lead Plastic Leaded Chip Carrier 44 Lead Ceramic Leaded Chip Carrier
Commercial Commercial Commercial
Industrial
Military Commercial
Industrial
Military
Switching Characteristics
Parameter Subgroups
VOH 1, 2, 3 VOL 1, 2, 3 VIH 1, 2, 3 VIL 1, 2, 3 IIX 1, 2, 3 IOZ 1, 2, 3 ICC1 1, 2, 3 Document #: 38-00212-E ABEL is a trademark of Data I/O Corporation. LOG/iC is a trademark of Isdata Corporation. CUPL is a trademark of Logical Devices Incorporated.
tPD tCO tICO tS tH tIS tIH tICS
9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11
9
7c371: Tuesday, May 26, 1992 Revision: August 9, 1995
CY7C371
Package Diagrams
44 Lead Thin Plastic Quad Flat Pack A44
44 Lead Plastic Leaded Chip Carrier J67
10
7c371: Tuesday, May 26, 1992 Revision: August 9, 1995
CY7C371
Package Diagrams (continued)
44 Pin Ceramic Leaded Chip Carrier Y67
E
Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice.
Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress Semiconductor Corporation product. Nor does it convey or imply any license under patent or other rights. Cypress Semicon ductor does not authorize its products for use as critical components in life support systems where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life support systems applications implies that the manufacturer assumes all risk of such use and in so doing indemnifies Cypress Semiconductor against all damages.
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